This invention relates generally to programmable logic integrated circuits device and, in particular, to a programmable logic integrated circuits device with an improved logic built-in block.
A programmable logic device (PLD) that is now widely used in various applications generally comprises a programmable logic built-in block or logic array. This logic array is usually made up of a programmable AND array whose outputs drive a OR array. A plurality of input lines are provided to the AND array, and a plurality of output lines are fed by the OR array to drive a plurality of macrocells of the device. Basically there are two kinds of structures of this programmable logic built-in block or logic array. The first one, known as Programmable Array Logic (PAL) structure, features a programmable AND array fixedly connecting to a set of OR gates, with each OR gate being driven by a fixed number of product terms. The second one, known as Programmable Logic Array (PLA) structure, features a programmable AND array selectively connecting to a fully programmable OR array. Both of the structures have their own strengths and weaknesses when used to implement different kinds of logic design.
Most of the programmable logic devices apply the PAL structure as their basic programmable logic array structure because of its short propagation delay and small die size. However the fixed nature of the product terms of the PAL structure also presents some problems. The amount of the product terms a logic design requires varies with the applications. If the required logic exceeds the amount the fixed product terms can offer, direct fitting is impossible, and re-design and re-fitting are required. If the required logic is less than the amount the fixed product terms can offer, the unused product terms are wasted since the logic allocation is fixed. To solve these problems, some PLDs of this structure employ a foldback AND array to form a group of shared expander product terms which could be fed back into the array for use by any or all of the dedicated product terms to expand the logic on an output. The use of these shared expander product terms could implement extremely wide gating functions. However the basic problem with foldback AND array is that it implements an extended logic in multiple levels that require multiple passes through the array. This will greatly increase the delay of a logic design. Furthermore, a multiple level design is much more difficult to synthesize. Other PLDs using the PAL structure employ a dynamic product term steering or parallel expander scheme that offers the logic allocation function between logic array and macrocells. This can eliminate the multiple level logic problems introduced by the foldback AND array mentioned above, and also provides a wide range of gating functions on an output. But a further problem exists with this structure is if some product terms in one cluster are steered to extend its neighboring macrocell, the unused product terms of this cluster and its corresponding macrocell will be wasted. In addition, to obtain more flexible logic allocation ability, the steering structure becomes more and more complex.
Some programmable logic devices apply the PLA structure as their basic programmable logic array structure. This structure completely eliminates the logic allocation problems associated with foldback AND array and product term steering mechanisms by employing a fully programmable OR array selectively connectable to the programmable AND array. The fully programmable OR array offers the ability to effectively and accurately allocate logic as a design requires, with the ability to share full product terms. The device re-fitting ability is only limited by the maximum capability of the device. Traditionally, however, the devices with these two fully programmable arrays are slower than the device with a PAL structure since signals have to pass through two arrays, and the main delay of the device is contributed by two arrays.
In view of the foregoing, it would be desirable to provide an improve programmable logic device architecture with both flexible and effective logic allocation feature and high speed feature.